Question:-
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages.
The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively.
Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?
Instruction

I0 :MUL R2 ,R0 ,R1

I1 :DIV R5 ,R3 ,R4

I2 : ADD R2 ,R5 ,R2

I3 :SUB R5 ,R2 ,R6

Meaning of instruction

R2 ¬ R0 *R1

R5 ¬ R3 /R4

R2 ¬ R5 +R2

R5 ¬ R2- R6
Option (A)
13
Option (B)
15
Option(C)
17
Option(D)
19
Correct Option:
(B)
Question Solution:
clocks.

So total 15 cycles required
question-answer-faq-2237