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Motivation
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1 Non-pipelined design
1 Single-cycle implementation
(I) The cycle time depends on the slowest instruction
(II) Every instruction takes the same amount of time
2 Multi-cycle implementation
(i) Divide the execution of an instruction into multiple steps
(II) Each instruction may take variable number of steps (clock cycles)
2 Pipelined design
(1) Divide the execution of an instruction into multiple steps (stages)
(2) Overlap the execution of different instructions in different stages
(I) Each cycle different instruction is executed in different stages
(II) For example, 5-stage pipeline (Fetch-Decode-Read-Execute-Write),
(i) 5 instructions are executed concurrently in 5 different pipeline stages
(ii) Complete the execution of one instruction every cycle (instead of every 5 cycle)
(iii) Can increase the throughput of the machine 5 times
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