Biasing MOSFET Amplifiers. MOSFET Current Mirrors.
There are two different environments in which MOSFET
amplifiers are found, (1) discrete circuits and (2) integrated
circuits (ICs). The methods of biasing transistor amplifiers are different in these two environments.Why? Primarily because it’s “expensive” t o fabricate resistors (and large capacitors) on ICs. Of course, this is not a problem
for discrete component circuits.We will discuss these two environments separately. Biasing Discrete MOSFET Amplifier Circuits
The methods we can use here are virtually identical to the BJT amplifier circuits we saw in Chapter 5. A few of these biasing topologies are:

Example N30.1. Design the MOSFET amplifier below so that
I_{D} =1 mA and allow for a drain voltage swing of ±2 V. The amplifier is to present a 1-M beta input resistance to a capacitively coupled input signal. The transistor has k_{n}^{’} W| L = 0.5 mA/V^{2} and V_{t} =2 V.

We can see directly from this circuit that at DC, V_{G} = 0. Recall that for operation in the saturation mode V_{GD}= V_{t} (with V_{GS} >0 ). Now, for 2 ± -V swing in vo and large AC gain, we want RD to be large. Hence, let’s choose V_{D} =0 (since V_{t} = 2V). Then for this ±2 -V swing in v_{0}
V _{GD}|_{max }=0-2=-2t
V_{GD}|_{max}=0+2 V =V_{t}
Because of these results, the MOSFET stays in saturation.
Consequently,

For a saturated MOSFET

For R _{D}=1 mA Þ (V_{GS} -2 )^{2}=4
Or
V_{GS} = + 2 + 2 +4 V or 0 V
With V _{G} =0 and V _{GS } =4 V then V 0 V

Lastly, for a 1-M. AC input resistance, then referring to the
input portion of the small-signal model

we see that
R_{in}=R_{G} Þ R_{G}=1 M beta Biasing IC MOSFET Amplifiers. Current Mirrors.
For MOSFET amplifier biasing in ICs, DC current sources are usually used. As discussed in Lecture 17, “golden currents” are produced using sophisticated multi-component circuits. Then current mirroring (aka current steering) circuits are used to replicate this golden current to provide DC biasing currents at different points in the IC.
The basic MOSFET current mirror is shown in Fig. 4.33b for NMOS. (This is basically the same circuit we saw with the BJT current mirror in )

Q1 has the drain and gate terminals connected together. This
forces Q1 to operate in the saturation mode in this particular
circuit if In this mode

With a zero gate current,
I _{REF}=I _{D1}
where we can easily see from the above circuit that

Now, we’ll assume the two MOSFETs in the circuit have the same VGS. Consequently, the drain current in the second
transistor is

If these two transistors are perfectly matched but perhaps
fabricated with different channel dimensions, then 1 2 n n k_{n1}^{ '}= K_{n2}^{’} , and V_{t1}= V_{t2} so that we see by comparing (1) and (4) that

In this NMOS current mirror shown above, Q2 acts as a current sink since it pulls current I_{0} =I_{D2} from the load, which is the amplifier circuit of in this case.In PMOS this current mirror circuit is constructed as

Here Q2 acts as a current source since it pushes current I_{0}I =I_{D2} into the load.
Example N30.2. Design an NMOS current mirror with V _{DD}= 5 V, VSS = 0, and I_{REF} =100 uA. For the matched transistors L =10 um , W =100 um, V_{t} = 1V, and 20 n k_{n}^{ ' = uA/V2. Referring to the NMOS current mirror circuit in Fig. 4.33b above, notice that the drain of Q1 is connected to its gate so that VGD1 = 1, which is less than Vt. This means Q1 is operating in the saturation mode (or is possibly cutoff).
Assuming operation in saturation,
For I REF=100 uA Þ 100=10.10(VGS-1)or V GD=+1+1=2V or 0 V
Now , by KVL
V DD=IREFR+VGS
With V GS=2V then
Here are a few additional questions based on this design:
• What is the lowest possible value for V0 =V2D and still have a functioning current mirror? As with Q1, the transistor Q2 must also operate in saturation if it’s going to supply a constant current.
Hence
V GD2£ V t Þ VG2-VD2£ V t
\ V 0= V D2 ³ V G2- V t
or V0 ³ V GS-Vt=2-1=1 V
Therefore,
V0|=1V
• Imagine that VA =107 L. (Notice that VA is proportional to the
channel length, which is commonplace.) What is ro?
VA =107.10*10-6=100 V
• What is change in the output current IO if VO changes by 3 V?
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