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Electronics II Tutorials
   Overview Analog Wireless Communcation
   Resistors, Capacitors, RC Networks
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   Impedance inverter
   Ideal Transformers
   Transformer shunt inductance
   BJT-Large signal models
   Transistor switches. Voltage regulators
   Transistor switches. Voltage regulators
   Common emitter amplifier. Max. efficiency of class A amps. Transformer coupled loads
   Available power. Distortion. Emitter degeneration. Miller effect
   Emitter follower and differential amplifiers
   JFET Source follower amplifier
   Oscillators. Clapp oscillator. VFO startup
   Variable frequency oscillator. Gain limiting
   Receiver incremental tuning. Crystal oscillators
   Mixers. Gilbert cell
   Superheterodyne receivers. Spurious responses of mixers
   Decreasing channel bandwidth by using CW
   Audio amplifiers
   JFETs as variable resistors
   Automatic gain control
   Noise, SNR, MDS, noise power density and NEP
   Nyquist noise formula. Cascading noisy components. Noise figure
   Receiver intermodulation and dynamic range
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Variable Frequency Oscillator Gain Limiting

Variable Frequency Oscillator Gain Limiting
The VFO is one of the main subsystems in a transceiver. It sets the operating frequency for both reception and transmission. In order to “tune” to other frequencies, we actually change the frequency of this variable frequency oscillator. Two general methods for making variable oscillators are:
1. Begin with a crystal oscillator and pass the signal through dividing or multiplication circuits to create sinusoids at other frequencies. This is called a synthesized source (like your Agilent 33120A).
2. Using an LC oscillator with a variable C and/or L. Synthesized sources often are very stable wrt temperature and other climate effects. However, these circuits are generally complex and expensive.
LC oscillators are often cheaper but can be less stable with temperature, humidity and other environmental changes. Our VFO uses a varactor in an LC oscillator to tune frequency. It is important that once a frequency is set for communication, the transceiver frequency should not vary (at least not too much).
Frequency Drift
In the NorCal 40A, the VFO operates at 2.1 MHz and is used as an input to the Transmit and RF Mixers

One reason for choosing a relatively “low” VFO frequency is that frequency drift is proportional to operating frequency. Hence, a lower f produces a smaller f drift per ºC change. Also, note that the VFO circuitry in the NorCal 40A is physically as far away as possible from the Power Amplifier. The PA generates most of the heat in the transceiver. The temperature coefficient ? of some quantity x is defined as

where T is the temperature (usually ºC). Your text lists temperature coefficients for many NorCal 40A components in Tables D.1 and D.2 on p. 356. (You can also find these coefficients in component data sheets.) For example:
• T68-7 core (for L9) has ? = +50 ppm/ºC,
• Polystyrene capacitors (C51-C53) have ? = ?150 ppm/ºC.
Note that ppm = parts per million = Hz/MHz for our purposes. These four components in the VFO have oppositely signed temperature coefficients! Consequently, these two competing effects help to reduce the frequency drift caused by temperature changes . Plus, polystyrene capacitors are largely immune to humidity changes.
Apparatus for Problems 27 and 29
In Prob. 27, you will measure the temperature coefficient ? for your VFO, and make an estimate of the expected value. An apparatus has been constructed to enclose your PCB when making these ? measurements. Warm your PCB with the heat gun through the holes on the sides of the container. Be careful not to melt the plastic container. To help with this, hold the heat gun back about 1 foot and wave it back and forth.

Gain Limiting
The VFO in the NorCal 40A is a Clapp oscillator, as shown in Fig. 11.4 and discussed in the last lecture. However, it turns out that the JFET amplifier is not overloaded, as sketched in order to obtain the gain condition |G |= |L |for oscillation. Instead, there is special gain limiting circuitry that has been added to the VFO to keep the JFET from overloading, but still allows the gain to vary with power level. This gain limiting circuit is formed from the diode, startup resistor and the divider capacitors C1 and C2 shown in

The purpose of the additional components are:
• Startup resistor (R21 = 47 k?): When the NorCal 40A is turned on, R21 ensures that the initial gate voltage is zero. This provides a large gm so that the oscillator starts easily [gm > 1/R ].
• Choke (RFC2 = 1 mH): This forces the DC value of the output voltage Vs equal to zero.
• Gain limiting diode (D9 = 1N4148): This diode only conducts for short periods of time when the sinusoidal gate voltage Vg is near positive peaks.
Considering this last component more carefully, when D9 conducts, current flows up through the divider caps C1 and C2, and then down through D. Consequently, charge is pulled from the caps leaving them with a net charge per cycle. This provides a negative dc voltage on the gate:

The caps will discharge through the startup resistor, but that time constant ? is much greater than T (=1/f = 1/2.1 MHz).
Gain Limiting Circuit Simulation
The gain of the JFET amplifier Q8 in the VFO is limited by the circuit shown in Fig. 11.6. In a simulation of the VFO circuit here, we’re going to use the It Sine transient current source in ADS, which is zero for t < 0 and a sinusoid for t > 0. This current source does not appear in the Nor Cal 40A VFO, and is used here only to illustrate how the capacitors C52 and C53 are charged up for gain limiting purposes.

The intended operation of this gain limiting circuit is for the ideal diode DIODE1 to conduct only for positive peaks in I1. The capacitors slowly charge up and over many periods of the current source reach a steady negative voltage, which is precisely what is needed to limit the gain of Q8. In the following result, we can see that the voltage across the two capacitors indeed becomes negative and constant with time:

Here are measurements from the actual VFO in the NorCal 40A:

The yellow trace is the source voltage of Q8, while the blue trace is the gate voltage. Note that this latter voltage has a negative average value, as predicted.
Operation of the Gain Limiting VFO Circuit
1. As long as gm > 1/R, the oscillation grows.
2. As the diode conducts current, it pulls charge through C1 and C2 thus reducing Vg (< 0) further.
3. As Vgs becomes more negative, gm decreases, as shown in

4. Eventually equilibrium is reached when the oscillation conditions |G| =|L| and ?G = ?L are satisfied. In this state, the output voltage oscillates and neither increases in amplitude nor decreases.
VFO Large Signal Analysis
The steady-state JFET source and gate voltages are sketched in above. This can be directly compared with the oscilloscope screen shot shown on page 7. As shown in the text, the large-signal oscillation condition is

where Gm is the large-signal transconductance of the JFET amplifier. It is defined as

where Id.pp and Vgs.pp are peak-to-peak values of the fundamental components (i.e., Fourier terms with frequency = 1?? ) of the drain current and the gate-to-source voltage, respectively. Our task now is to compute the p-t-p values of these fundamental frequency components so we can determine Gm. In our VFO, C1 = C2 so that from Vg 2Vs Because of the choke, Vs has zero dc value, whereas Vg has a dc value of Vb (< 0) due to the gain limiting circuit.It turns out that Vb is smaller than the pinch off voltage Vc of the JFET, as shown in

Consequently, this amplifier is operated in class C! The transistor is either on or off. If we approximate Vgs as

then during the “on” times of the JFET

It is this cosine-squared shape that is sketched above in The dc value of the drain current Io in the VFO JFET is


As shown in Section B.4 from a Fourier series expansion of a cosine square function, the p-t-p amplitude of the fundamental component is four times the dc value:
Idpp = 4? I0 ? Im
In words, (11.38) means that the p-t-p fundamental current component (i.e., a 2.1-MHz sinusoidal current) of the VFO JFET drain current, Idpp, is simply equal to Im. Now, we divide (11.38) by spp which is the p-t-p output (i.e., JFET source) voltage and find

contains a plot of (apparently) Idss and Vc for some particular JFET:

In Prob. 27.B you will use to predict Vs pp for a particular load resistance (since Gm = 1/R). (I didn’t obtain very good results for this part.)

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