Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give out sum and carry as output. Basically we have two types of adders.

Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This operation is called half addition and the circuit to realize it is called a half adder.

Truth Table

 X Y SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

Symbol

S (X,Y) = å (1,2)
S = X'Y + XY'
S = XÅY
CARRY(X,Y) = å (3)
CARRY = XY

Circuit

Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.

Truth Table

 X Y Z SUM CARRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

SUM (X,Y,Z) = å (1,2,4,7)
CARRY (X,Y,Z) = å (3,5,6,7)
Kmap-SUM

SUM = X'Y'Z + XY'Z' + X'YZ'
SUM = X ÅY ÅZ

Kmap-CARRY

CARRY = XY + XZ + YZ

The below implementation shows implementing the full adder with AND-OR gates, instead of using XOR gates. The basis of the circuit below is from the above Kmap.

Circuit-SUM

Circuit-CARRY

Circuit-SUM

Circuit-CARRY

An n-bit adder used to add two n-bit binary numbers can be built by connecting n full adders in series. Each full adder represents a bit position j (from 0 to n-1).
Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at higher position j+1. The output of a full adder at position j is given by: Sj= Xj ÅYj ÅCj
Cj+1 = Xj . Yj + Xj . Cj + Y . Cj
In the expression of the sum Cj must be generated by the full adder at lower position j. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:

Total Propagation delay = 2 nD

X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3
Total Propagation delay = 2 nD = 8D or 8 gate delays

Example: 16-bit adder using 4 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most significant position.

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder
= 4 x 2 nD = 4 x 8D = 32 D
or 32 gate delays

The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next. For large values of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved. Once these bits are available to the rest of the circuit, each individual three-bit addition (Xi+Yi+carry-ini) is implemented by a simple 3-input XOR gate. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate. For each input bits pair these functions are defined as:

Gi = Xi . Yi
Pi = Xi + Yi
The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the corresponding function Gi is '1' or if the c-out(i-1)='1' and the function Pi = '1' simultaneously. In the first case, the carry bit is activated by the local conditions (the values of Xi and Yi). In the second, the carry bit is received from the less significant elementary addition and is propagated further to the more significant elementary addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according to the equation:
carry_out(i) = Gi + Pi.carry_in(i-1)
For a four-bit adder the carry-outs are calculated as follows
carry_out0 = G0 + P0 . carry_in0
carry_out1 = G1 + P1 . carry_out0 = G1 + P1G0 + P1P0
carry_in0
carry_out2 = G2 + P2G1 + P2P1G0 + P2P1P0 . carry_in0
carry_out3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1
carry_in0
The set of equations above are implemented by the circuit below and a complete adder with a look-ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic gates in its counterparts illustrated earlier.

Sums can be calculated from the following equations, where carry_out is taken from the carry calculated in the above circuit.
sum_out0 = X 0Å Y0Å carry_out0
sum_out1 = X 1Å Y1Å carry_out1
sum_out2 = X 2Å Y2Å carry_out2
sum_out3 = X 3Å Y3Å carry_out3

BCD addition is the same as binary addition with a bit of variation: whenever a sum is greater than 1001, it is not a valid BCD number, so we add 0110 to it, to do the correction. This will produce a carry, which is added to the next BCD position.
· Add the two 4-bit BCD code inputs.
Determine if the sum of this addition is greater than 1001; if yes, then add 0110 to this sum and generate a carry to the next decimal position

Subtracter
Subtracter circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of Adder). There are two types of subtracters.

· Half Subtracter.
· Full Subtracter

Half Subtracter
The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol and truth table are shown below.

Symbol

Truth Table

 X Y D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

From the above table we can draw the Kmap as shown below for "difference" and "borrow". The boolean expression for the difference and Borrow can be written.

From the equation we can draw the half-subtracter as shown in the figure below.