# Digital logic families tutorials

Digital logic families tutorials

Logic families can be classified broadly according to the technologies they are built with. In earlier days we had vast number of these technologies, as you can see in the list below.
· DL : Diode Logic.
· RTL : Resistor Transistor Logic.
· DTL : Diode Transistor Logic.
· HTL : High threshold Logic.
· TTL : Transistor Transistor Logic.
· I2L : Integrated Injection Logic.
· ECL : Emitter coupled logic.
· MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
· CMOS : Complementary Metal Oxide Semiconductor Logic.
· Among these, only CMOS is most widely used by the ASIC (Chip) designers; we will still try to understand a few of the extinct / less used technologies. More in-depth explanation of CMOS will be covered in the VLSI section.

Basic Concepts
Before we start looking at the how gates are built using various technologies, we need to understand a few basic concepts. These concepts will go long way i.e. if you become a ASIC designer or Board designer, you may need to know these concepts very well.

· Fan-in.
· Fan-out.
· Noise Margin.
· Power Dissipation.
· Gate Delay.
· Wire Delay.
· Skew.
· Voltage Threshold

Fan-in
Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS based gate. Normally delay increases following a quadratic function of fan-in. Fan-out
The number of gates that each gate can drive, while providing voltage levels in the guaranteed range, is called the standard load or fan-out. The fan-out really depends on the amount of electric current a gate can source or sink while driving other gates. The effects of loading a logic gate output with more than its rated fan-out has the following effects.

· In the LOW state the output voltage VOL may increase above VOLmax.
· In the HIGH state the output voltage VOH may decrease below VOHmin.
· The operating temperature of the device may increase thereby reducing the reliability of the device and eventually causing the device failure.
· Output rise and fall times may increase beyond specifications
· The propagation delay may rise above the specified value.
· Normally as in the case of fan-in, the delay offered by a gate increases with the increase in fan-out. Gate Delay
Gate delay is the delay offered by a gate for the signal appearing at its input, before it reaches the gate output. The figure below shows a NOT gate with a delay of "Delta", where output X' changes only after a delay of "Delta". Gate delay is also known as propagation delay. Gate delay is not the same for both transitions, i.e. gate delay will be different for low to high transition, compared to high to low transition.
Low to high transition delay is called turn-on delay and High to low transition delay is called turn-off delay.

Wire Delay
Gates are connected together with wires and these wires do delay the signal they carry, these delays become very significant when frequency increases, say when the transistor sizes are sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight time from point A to B). Wire delay is also known as transport delay. Skew
The same signal arriving at different parts of the design with different phase is known as skew. Skew normally refers to clock signals. In the figure below, clock signal CLK reaches flip-flop FF0 at time t0, so with respect to the clock phase at the source, it has at FF0 input a clock skew of t0 time units. Normally this is expressed in nanoseconds. The waveform below shows how clock looks at different parts of the design. We will discuss the effects of clock skew later. Logic levelsc
Logic levels are the voltage levels for logic high and logic low.
· VOHmin : The minimum output voltage in HIGH state (logic '1'). VOHmin is 2.4 V for TTL and 4.9 V for CMOS.
· VOLmax : The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4 V for TTL and 0.1 V for CMOS.
· VIHmin : The minimum input voltage guaranteed to be recognised as logic 1. VIHmin is 2 V for TTL and 3.5 V for CMOS.
· VILmax : The maximum input voltage guaranteed to be recognised as logic 0. VILmax is 0.8 V for TTL and 1.5 V for CMOS.

Current levels
· IOHmin: The maximum current the output can source in HIGH state while still maintaining the output voltage above VOHmin.

· IOLmax : The maximum current the output can sink in LOW state while still maintaining the output voltage below VOLmax.
· IImax : The maximum current that flows into an input in any state (1mA for CMOS).

Noise Margin
Gate circuits are constructed to sustain variations in input and output voltage levels. Variations are usually the result of several different factors.

· Batteries lose their full potential, causing the supply voltage to drop
· High operating temperatures may cause a drift in transistor voltage and current characteristics
· Spurious pulses may be introduced on signal lines by normal surges of current in neighbouring supply lines
All these undesirable voltage variations that are superimposed on normal operating voltage levels are called noise. All gates are designed to tolerate a certain amount of noise on their input and output ports. The maximum noise voltage level that is tolerated by a gate is called noise margin. It derives from I/P-O/P voltage characteristic, measured under different operating conditions. It's normally supplied from manufacturer in the gate documentation.
· LNM (Low noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level when superimposed on the input voltage of the logic gate (when this voltage is in the LOW interval). LNM=VILmax-VOLmax.
· HNM (High noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level if superimposed on the input voltage of the logic gate (when this voltage is in the HIGH interval). HNM=VOHmin-VIHmin.

tr (Rise time)
The time required for the output voltage to increase from VILmax to VIHmin.

tf (Fall time)
The time required for the output voltage to decrease from VIHmin to VILmax.

tp (Propagation delay)
The time between the logic transition on an input and the corresponding logic transition on the output of the logic gate. The propagation delay is measured at midpoints.

Power Dissipation.
Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a certain amount of current during its operation. Since each gate can be in a High, Transition or Low state, there are three different currents drawn from power supply.

· ICCH: Current drawn during HIGH state.
· ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
· ICCL: Current drawn during LOW state.
For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency.
Power Dissipation is an important metric for two reasons. The amount of current and power available in a battery is nearly constant. Power dissipation of a circuit or system defines battery life: the greater the power dissipation, the shorter the battery life. Power dissipation is proportional to the heat generated by the chip or system; excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range; will cause gates to generate improper output values. Thus power dissipation of any gate implementation must be kept as low as possible.
Moreover, power dissipation can be classified into Static power dissipation and Dynamic power dissipation.
· Ps (Static Power Dissipation): Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
· Pd (Dynamic Power Dissipation): Power consumed during output and input transitions. So we can say Pd is the actual power consumed i.e. the power consumed by transistors + leakage current.
Thus
Total power dissipation = static power dissipation + dynamic power dissipation.

Diode Logic
In DL (diode logic), all the logic is implemented using diodes and resistors. One basic thing about the diode, is that diode needs to be forward biased to conduct. Below is the example of a few DL logic circuits. When no input is connected or driven, output Z is low, due to resistor R1. When high is applied to either X or Y, or both X and Y are driven high, the corresponding diode get forward biased and thus conducts. When any diode conducts, output Z goes high.

Points to Ponder
· Diode Logic suffers from voltage degradation from one stage to the next.

· Diode Logic only permits OR and AND functions.
· Diode Logic is used extensively but not in integrated circuits.

Resistor Transistor Logic
In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. One basic thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. like a inverter). Below is the example of a few RTL logic circuits. A basic circuit of an RTL NOR gate consists of two transistors Q1 and Q2, connected as shown in the figure above. When either input X or Y is driven HIGH, the corresponding transistor goes to saturation and output Z is pulled to LOW.

Diode Transistor Logic
In DTL (Diode transistor logic), all the logic is implemented using diodes and transistors. A basic circuit in the DTL logic family is as shown in the figure below. Each input is associated with one diode. The diodes and the 4.7K resistor form an AND gate. If input X, Y or Z is low, the corresponding diode conducts current, through the 4.7K resistor. Thus there is no current through the diodes connected in series to transistor base . Hence the transistor does not conduct, thus remains in cut-off, and output out is High.

If all the inputs X, Y, Z are driven high, the diodes in series conduct, driving the transistor into saturation. Thus output out is Low. Transistor Transistor Logic
In Transistor Transistor logic or just TTL, logic gates are built only around transistors. TTL was developed in 1965. Through the years basic TTL has been improved to meet performance requirements. There are many versions or families of TTL.

· Standard TTL.
· High Speed TTL
· Low Power TTL.
· Schhottky TTL.
Here we will discuss only basic TTL as of now; maybe in the future I will add more details about other TTL versions. As such all TTL families have three configurations for outputs.
· Totem - Pole output.
· Open Collector Output.
· Tristate Output.
Before we discuss the output stage let's look at the input stage, which is used with almost all versions of TTL. This consists of an input transistor and a phase splitter transistor. Input stage consists of a multi emitter transistor as shown in the figure below. When any input is driven low, the emitter base junction is forward biased and input transistor conducts. This in turn drives the phase splitter transistor into cut-off. Totem - Pole Output
Below is the circuit of a totem-pole NAND gate, which has got three stages.

· Input Stage
· Phase Splitter Stage
· Output Stage
Input stage and Phase splitter stage have already been discussed. Output stage is called Totem-Pole because transistor Q3 sits upon Q4.
Q2 provides complementary voltages for the output transistors Q3 and Q4, which stack one above the other in such a way that while one of these conducts, the other is in cut-off.
Q4 is called pull-down transistor, as it pulls the output voltage down, when it saturates and the other is in cut-off (i.e. Q3 is in cut-off). Q3 is called pull-up transistor, as it pulls the output voltage up, when it saturates and the other is in cut-off (i.e. Q4 is in cut-off).
Diodes in input are protection diodes which conduct when there is large negative voltage at input, shorting it to the ground. Tristate Output.
Normally when we have to implement shared bus systems inside an ASIC or externally to the chip, we have two options: either to use a MUX/DEMUX based system or to use a tri-state base bus system.

In the latter, when logic is not driving its output, it does not drive LOW neither HIGH, which means that logic output is floating. Well, one may ask, why not just use an open collector for shared bus systems? The problem is that open collectors are not so good for implementing wire-ANDs.
The circuit below is a tri-state NAND gate; when Enable En is HIGH, it works like any other NAND gate. But when Enable En is driven LOW, Q1 Conducts, and the diode connecting Q1 emitter and Q2 collector, conducts driving Q3 into cut-off. Since Q2 is not conducting, Q4 is also at cut-off. When both pull-up and pull-down transistors are not conducting, output Z is in high-impedance state. Note : I will try to add more details when I find time

Integrated Injection Logic
Emitter coupled logic
Emitter coupled logic (ECL) is a non saturated logic, which means that transistors are prevented from going into deep saturation, thus eliminating storage delays. Preventing the transistors from going into saturation is accomplished by using logic levels whose values are so close to each other that a transistor is not driven into saturation when its input switches from low to high. In other words, the transistor is switched on, but not completely on. This logic family is faster than TTL.

Voltage level for high is -0.9 Volts and for low is -1.7V; thus biggest problem with ECL is a poor noise margin.
A typical ECL OR gate is shown below. When any input is HIGH (-0.9v), its connected transistor will conduct, and hence will make Q3 off, which in turn will make Q4 output HIGH.
When both inputs are LOW (-1.7v), their connected transistors will not conduct, making Q3 on, which in turn will make Q4 output LOW. Metal Oxide Semiconductor Logic
MOS or Metal Oxide Semiconductor logic uses nmos and pmos to implement logic gates. One needs to know the operation of FET and MOS transistors to understand the operation of MOS logic circuits.

The basic NMOS inverter is shown below: when input is LOW, NMOS transistor does not conduct, and thus output is HIGH. But when input is HIGH, NMOS transistor conducts and thus output is LOW. Normally it is difficult to fabricate resistors inside the chips, so the resistor is replaced with an NMOS gate as shown below. This new NMOS transistor acts as resistor. Complementary Metal Oxide Semiconductor Logic
CMOS or Complementary Metal Oxide Semiconductor logic is built using both NMOS and PMOS. Below is the basic CMOS inverter circuit, which follows these rules:

· NMOS conducts when its input is HIGH.
· PMOS conducts when its input is LOW.
· So when input is HIGH, NMOS conducts, and thus output is LOW; when input is LOW PMOS conducts and thus output is HIGH. 